In general, the particles found in various radiative environments (for example, the space or atmospheric radiative environment) interact with the materials comprising an integrated circuit, in particular semiconductor materials (for example, silicon).
The effects of the impact of a charged particle on an integrated circuit can be divided into two categories: cumulative effects (or dose effects) capable of modifying the electrical characteristics of the component (threshold voltage, transistor gain, etc.) and singular effects (or SEE, for “Single Event Effects”).
The disadvantages of the prior art are discussed below in the particular case of SET (“Single Event Transient”) singular effects on a NOT-AND logic gate.
It is noted that a SET, also referred to as a transient voltage pulse or transient variable, is initiated when an ionising particle hits the blocked junction of a MOSFET transistor. Generally, the passage of an ionising particle (for example, a heavy ion) through the inverted polarised junction of a transistor results in the creation of electron-hole pairs in a zone centred on the track of the incident particle. These electron-hole pairs can modify the distribution of the electric field in the substrate, thus causing a collection by drift of electrons and holes. This mechanism of collection by drift, also referred to below as “funelling”, may cause the appearance of a transient voltage pulse (SET).
In reference to FIG. 1a, the impact mechanisms (of a heavy ion) for the case of a NOT-AND logic gate are described.
For the sake of simplification of the description, this document will hereinafter describe only the specific case of integrated circuits operating under reference voltages 0 V and 3 V. A person skilled in the art can easily extend this teaching to any type of voltage intended to power an integrated electronic circuit.
The NOT-AND logic gate 100 receives, at a first input 1, a first command voltage VCOM 1, and, at a second input 2, a second command voltage VCOM2, and generates, at the output 3, a resulting voltage VNAND.
This NOT-AND logic gate 100 itself includes a transistor TN1, of which the gate GN1 forms the first input 1 (to which the first command voltage VCOM1 is directly applied) and of which the drain DN1 is connected to the output 3, and a transistor TN2, of which the gate GN2 forms the second input 2 (to which the second command voltage VCOM2 is applied). The source SN2 of the transistor TN2 is connected to the reference potential VSS (also referred to as low level in the rest of the description), for example of 0 V, and the drain DN2 of transistor TN2 is connected to the source SN1 of transistor TN1.
The NOT-AND logic gate 100 also includes two transistors TP1 and TP2, of which the gates GP1 and GP2 respectively receive the first command voltage VCOM1 and the second command voltage VCOM2. The sources SP1 and SP2 of the transistors TP1 and TP2 are connected to the power supply VCC of the circuit (also referred to as high level in the rest of the description), for example of 3 V, and their drains DP1 and DP2 are connected to the drain DN1 of transistor TN1.
Thus, when the first and second command voltages VCOM1 and VCOM2 are substantially equal to the power supply VCC, i.e. 3 V, then the resulting voltage VNAND, generated at the output 3, is substantially equal to the reference potential VSS, i.e. 0 V.
Conversely, when the first command voltage VCOM1 or (and) the second command voltage VCOM2 is (are) substantially equal to the reference potential VSS, i.e. 0 V, then the resulting voltage VNAND, generated at the output 3, is substantially equal to the power supply VCC, i.e. 3 V.
As indicated above, a heavy ion can create a transient variable at the output 3 of the NOT-AND logic gate 100.
Indeed, in a first impact case, in which the transistors TP1 and TP2 are both in an off state (i.e. when the command voltages VCOM1 and VCOM2 are equal to 3 V), if a heavy ion 10 hits transistor TP1, then a transient voltage pulse appears at the output 3. This pulse, also called low-to-high pulse, corresponds to the successive switchings of the resulting voltage VNAND from 0 V (low level) to 3 V (high level), then from 3 V to 0 V.
In a second impact case, in which the transistors TP1 and TP2 are both in an off state (i.e. when the command voltages VCOM1 and VCOM2 are equal to 3 V), if a heavy ion 10 hits transistor TP2, then a low-to-high pulse appears at the output 3.
Then, in a third impact case, in which the transistor TN1 is in an off state (i.e. when the command voltage VCOM1 is equal to 0 V) and the transistor TN2 is in an on state (i.e. when the command voltage VCOM2 is equal to 3 V), if a heavy ion 10 hits the transistor TN1, then a transient voltage pulse appears at the output 3. This pulse, also called high-to-low pulse, corresponds to the successive switches of the resulting voltage VNAND from 3 V (high level) to 0 V (low level), then from 0 V to 3 V.
Finally, in a fourth impact case, in which the transistor TN2 is in an off state (i.e. when the command voltage VCOM2 is equal to 0 V) and the transistor TN1 is in an on state (i.e. when the command voltage VCOM1 is equal to 3 V), if a heavy ion 10 hits the transistor TN2, then a high-to-low pulse appears at the output 3.
These transient voltage pulses generated at the output 3 of the NOT-AND gate 100 can cause a logic error, leading to a critical failure of the system in which the logic gate 100 is implemented.
A well-known technique for preventing the propagation of erroneous information (i.e. a SET) in a set of cascade-mounted logic cells is based on the use of intermediate transistors.
This hardening technique consists of providing two redundant outputs and placing a set of intermediate PMOS and NMOS transistors between a first transistor block, including only PMOS transistors, and a second transistor block, including only NMOS transistors, so as to distinguish the first block from the second block.
In other words, this set of intermediate transistors makes it possible not to propagate a SET appearing at the output of the first block to the output of the second block, and the inverse.
In relation to FIG. 1b, a cell of this type, known as a “Dual Stream Redundancy”, referenced 200, will now be described.
As will be seen, in all of the figures of this document, the same elements are designated with the same numeric reference.
The “Dual Stream” cell 200 includes a pair of intermediate transistors 202 placed between a first PMOS transistor block 201 and a second NMOS transistor block 203.
The first PMOS transistor block 201 includes transistors TP1 and TP2 of the NOT-AND logic gate 100 (FIG. 1a). The sources SP1 and SP2 of transistors TP1 and TP2 are connected to the power supply VCC of the circuit and their drains DP1 and DP2 are mutually connected, so as to form a first output 4, also called path P in the description below.
The second NMOS transistor block 203 includes transistors TN1 and TN2 of the NOT-AND logic gate 100 (FIG. 1a). The source SN2 of transistor TN2 is connected to the reference potential VSS and its drain DN2 is connected to the source SN1 of transistor TN1, of which the drain DN1 forms a second output 5, also called path N in the description below.
The pair of intermediate transistors 202 includes a first intermediate transistor TN3, of which the gate GN3 is connected to the first output 4 and the drain DN3 is connected to the second output 5. The source SN3 of the transistor TN3 is connected to the power supply VCC.
The pair of intermediate transistors 202 also includes a second intermediate transistor TP3, of which the gate GP3 is connected to the second output 5 (path N) and the drain DP3 is connected to the first output 4 (path P). The source SP3 of transistor TP3 is connected to the reference potential VSS.
For the sake of clarity, only the operation of the dual stream cell for various values of the first command voltage VCOM1 and for a second command voltage VCOM2 equal to the power supply VCC will be described below.
When the second command voltage VCOM2 is equal to 3 V, transistor TP2 is placed in an off state (open switch) and transistor TN2 is placed in an on state (closed switch), in which it connects the source of the transistor TN1 to the reference potential VSS.
FIG. 2a shows the simplified diagram of the dual stream cell 200 for the case in which the first command voltage VCOM1 is equal to the reference potential VSS. When the first command voltage VCOM1 is equal to 0 V, the transistor TN1 is placed in an off state and transistor TP1 is placed in an on state, in which it polarises the gate GN3 of the intermediate transistor TN3 with a high level, i.e. 3 V. The intermediate transistor TN3 is therefore in an on state, in which it sets the output voltage VNOUT, generated on the path N, at a high degraded level (i.e. at a level equal to the difference between the high level of 3 V and the threshold voltage of the transistor (generally 0.7 V)). The vertical PN (junction) diode D1 of the input transistor TN1 is inversely polarised. When an ionising particle 10 (or heavy ion) passes through, the funnelling phenomenon short-circuits the diode D1 and causes the transient change in the output voltage VNOUT from 3 V (high level) to 0 V (low level). Due to the presence of the intermediate transistor TN3, placed between path P and path N, the high-to-low pulse (SET) generated on path N is not propagated to path P. The output voltage VPOUT, generated on path P, remains unaffected, i.e. equal to the power supply VCC of 3 V (because the transistor TP1 is on).
FIG. 2b shows the simplified diagram of the dual stream cell 200 for the case in which the first command voltage VCOM1 is equal to the power supply VCC. When the first command voltage VCOM1 is equal to 3 V, the transistor TP1 is placed in an off state and transistor TN1 is placed in an on state, in which it polarises the gate GP3 of the intermediate transistor TP3 with a low level, i.e. 0 V. The intermediate transistor TP3 is therefore in an on state, in which it sets the output voltage VPOUT, generated on the path P, at a low degraded level (i.e. at a level equal to the threshold voltage of the transistor, 0.7 V). The vertical PN Function) diode D2 of the input transistor TP1 is inversely polarised. When an ionising particle 10 (or heavy ion) passes through, the funnelling phenomenon short-circuits the diode D2 and causes the transient change in the output voltage VPOUT from 0 V (low level) to 3 V (high level). Due to the presence of the intermediate transistor TP3, placed between path P and path N, the low-to-high pulse (SET) generated on path P is not propagated to path N. The output voltage VNOUT, generated on path N, remains unaffected, i.e. equal to the reference potential VSS of 0 V (because the transistor TN1 is on).
When the intermediate transistors TN3 and TP3 are impacted by an ionising particle when they are off (TN3 if off when VCOM1 is at the high level and TP3 is off when VCOM1 is at the low level), the absence of voltage at the terminals of the vertical PN diodes D1 and D2 of transistors TN1 and TP1 prevents the funnelling phenomenon and the transient pulses generated on paths N and P are then very weak. In this case, the charges are evacuated by recombination.
Thus, this dual stream cell makes it possible to maintain the high-to-low pulses on path N and the low-to-high pulses on path P. In other words, in the case of impact by an ionising particle, the dual stream cell allows either the change in the output voltage VNOUT to the low level or the change in the output voltage VPOUT to the high level.
The dual stream cell is therefore insensitive to SETs because it enables non-erroneous information to be delivered on at least one path P or N.
As shown in FIG. 1c, the dual stream cell 200 can be connected to an inverter 300 itself including two transistors TP4 and TN4, of which the gates GP4 and GN4 respectively receive the output voltages VPOUT and VNOUT, so that:
when the voltage VPOUT is at the low level, the transistor TP4 is placed in an on state, in which it sets the output voltage (not shown) at the high level, i.e. 3 V;
when the voltage VNOUT is at the high level, the transistor TN4 is placed in an on state, in which it sets the output voltage (not shown) at the low level, i.e. 0 V.
Thus, when the output voltages VPOUT and VNOUT have short disturbances (SET), it is possible to have a high-impedance output configuration in which the inverter memorises the current state of the output voltage (no change in the output voltage).
This dual stream cell has shown significant progress in integrated circuit hardening mechanisms. However, it has a certain number of disadvantages.
First, this solution of the prior art has an excessive static electrical consumption. Indeed, the intermediate transistors TP3 and TN3 respectively transmit a degraded low level on path P and a degraded high level on path N.
In reference to FIG. 3a, when the first command voltage VCOM1 is equal to the low level, the transistor TP1 polarises the gate GN3 of the intermediate transistor TN3. The latter, of which the source SN3 is connected to the power supply VCC of the circuit, transmits, on its drain DN3, a slightly degraded high level 6, leading to a very slight saturation of the intermediate transistor TP3. This very slight saturation will therefore create a direct path 7 between the power supply and the reference potential, thus causing an increase in the current consumption.
The term “degraded level” refers to a level offset by the threshold voltage of the transistor.
Conversely, an as shown in FIG. 3b, when the first command voltage VCOM1 is equal to the high level, the transistor TN1 polarises the gate GP3 of the intermediate transistor TP3. The latter, of which the source SP3 is connected to the reference potential VSS of the circuit, transmits, on its drain DP3, a slightly degraded low level 8, leading to a very slight saturation of the intermediate transistor TN3. This very slight saturation will therefore create a direct path 9 between the power supply and the reference potential, thus causing an increase in the current consumption.
As already indicated (FIG. 1c), the dual stream cell must be mounted in series with an inverter, so as to be capable of restoring a non-disturbed output signal.
Another major disadvantage of this technique therefore lies in the fact that the inverter is sensitive to the impact of the ionising particles.